The disclosed embodiments of the present invention relate to a differential sensing circuit, and more particularly, to a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory.
About a conventional single-ended sensing circuit for a single-ended bit line memory, in order to ensure noise immune operation, the conventional single-ended sensing circuit requires that the bit line is discharged fully (rely on the trip voltage of an inverter, wherein a sense margin is about 0.5 VCC). For this reason, the conventional single-ended sensing circuit reads are typically slower than differential sensing reads. About another conventional single-ended sensing circuit for a single-ended bit line memory, in order to have high performance design, the conventional single-ended sensing circuit adopts large signal sensing feature domino style hierarchical bit lines (i.e. short local read bit-lines). However, the conventional single-ended sensing circuit results in a high power consumption problem.
In addition, please refer to FIG. 1. FIG. 1 is a conventional differential sensing circuit 100 for a single-ended bit line memory. As shown in FIG. 1, the conventional differential sensing circuit 100 comprises: a voltage down converter 102, a reference voltage generator 104 and a differential sensing amplifier 106. However, the conventional differential sensing circuit 100 needs the global voltage down converter 102 to generate the voltage reference for the differential sensing amplifier 106, wherein the global voltage down converter 102 suffers a DC current and requires a larger chip area.